The present invention relates generally to time reference devices and methods to synchronize signals and processes in distributed digital processor systems. More particularly, the present invention relates to a unique, highly accurate distributed time reference device and method for serial communications systems that support distributed digital processors.
Presently, there are several different types of multiplexed communication buses in existence which provide a means to distribute digital processors. Each of these bus structures typically has a control interface which includes some method for time synchronization. An example of one such bus structure used in military applications is the military standard MIL-STD-1553 type bus structure. Like most bus structures, MIL-STD-1553 includes interface standards and has a defined bus controller mode of operation. While this bus structure provides a natural distribution network for time synchronization across the system, this bus structure, as well as most other bus structures, lacks a highly accurate time synchronization ability as related to distributed processing. This is primarily due to the location of the time reference relative to the processing unit and the method of alignment of the time reference devices in a distributed processing system.
Other methods used for time synchronization employ a dedicated bus to distribute a synchronizing pulse which starts free running timers periodically. The free running timers drift over time, but are resynchronized (reset) with each synchronizing pulse. Absolute time may be kept by using a master timer to generate the pulses as the value (i.e. binary) changes from all 1's to all 0's. Each processor in the distributed processing system has its own timer. The alignment of the collective time reference system is limited by the time of propagation of the synchronizing pulse and the drift rate between each pulse. Therefore, such systems must use very high frequency counters with highly stable and accurate clocking signals to assure the desired instantaneous alignment accuracies. Accordingly, there exists a need in the art for a device and method which synchronizes distributed processors without the need for an additional transmission system or additional highly accurate clocking signals. The present invention addresses such a need.
Other timing mechanisms used in MIL-STD-1553 interfaces are used for controlling cyclic data transfers. An example of such a timing mechanism is described in U.S. Pat. No. 5,367,641 issued to Pressprich, et. al. on Nov. 22, 1994 and entitled, "MIL-STD-1553 Interface Device Having A Bus Controller Minor Frame Timer." The invention described in this patent includes an integrated circuit (IC) which interfaces a piece of communications equipment to a MIL-STD-1553 bus in accordance with the MIL-STD-1553 interface standards and operates in the MIL-STD-1553 defined bus controller mode of operation. The IC implements a command block configuration of data storage locations in an external memory. The command block includes a plurality of words arranged contiguously, including a first word indicative of one of a plurality of different opcodes that define the operation of the IC. The command block words include a MIL-STD-1553 defined command to be transmitted on the bus by the IC. A plurality of command blocks are arranged contiguously in a minor frame format. In order to sequentially execute a plurality of minor frames at different frequencies, the IC contains an internal timer that controls the execution time of each minor frame. The first command block of each minor frame contains an opcode that loads the timer with a predetermined value for the corresponding frequency of execution of the particular minor frame. The timer counts down and decrements to zero before it is loaded with a value for execution frequency of the next minor frame. While the timer is decrementing, the IC executes the command blocks that follow the first command block. Those skilled in the art will appreciate that while this invention will be useful in several specific applications, it requires a specialized protocol and/or sequencing of the signal. Accordingly, the invention described in U.S. Pat. No. 5,367,641 may not be used for general applications.